1. Field
The embodiment(s) discussed herein relates to the layout design of a semiconductor integrated circuit and a layout design method.
2. Description of the Related Art
The number of inputs/outputs (I/Os) has increased along with miniaturization in the process technology of semiconductor integrated circuits and functional upgrading in semiconductor integrated circuits. Thus, the area of a semiconductor integrated circuit is determined by the configuration and the quantity of I/O circuits. Accordingly, a technique of reducing the area of a semiconductor integrated circuit by the layout of I/O circuits is discussed in, for example, Japanese Patent No. 2720629, Japanese Laid-open Patent Publication No. H5-259379, and Japanese Laid-open Patent Publication No. H5-326712.
The area of a semiconductor integrated circuit is also determined by the area of a core region. Such determination is referred to as core regulation. Layout design compliant with core regulation is discussed in, for example, Japanese Laid-open Patent Publication No. 2007-96216.